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9-mb (256k x 32) pipelined dcd sync sra m cy7c1368 b cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05419 rev. ** revised december 23, 2003 features ? registered inputs and outputs for pipelined operation optimal for performance (double-cycle deselect) ? depth expansion without wait state 256k 32-bit common i/o architecture 3.3v ?5% and +10% core power supply (v dd ) 3.3v i/o supply (v ddq ) fast clock-to-output times ? 3.0 ns (for 200-mhz device) ? 3.5 ns (for 166-mhz device) provide high-performance 3-1-1-1 access rate user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences multiple chip enables for depth expansion: three chip enables for a package version and two chip enables for aj package version separate processor and controller address strobes synchronous self-timed writes asynchronous output enable jedec-standard 100-pin tqfp package and pinout ?zz? sleep mode option functional description [1] the cy7c1368b sram integrates 262,144 x 32 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable ( ce 1 ), depth-expansion chip enables (ce 2 and ce 3 [2] ), burst control inputs ( adsc , adsp , and adv ), write enables ( bw a , bw b , bw c , bw d and bwe ), and global write ( gw ). asynchronous inputs include the output enable ( oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor ( adsp ) or address strobe controller ( adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin ( adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to four bytes wide as controlled by the byte write control inputs. gw active low causes all bytes to be written. this device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.this feature allows depth expansion without penal- izing system performance. the cy7c1368b operates from a +3.3v core power supply and a +3.3v supply for the i/os. all inputs and outputs are jedec-standard jesd8-5-compatible. notes: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. 2. ce 3 is for a version (3 chip enable option) only selection guide 200 mhz 166 mhz unit maximum access time 3.0 3.5 ns maximum operating current 220 180 ma maximum cmos standby current 30 30 ma
cy7c1368 b document #: 38-05419 rev. ** page 2 of 17 functional block diagram?256kx32 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bw d bw c bw b bw a bwe gw ce 1 ce 2 ce 3 oe dq d byte write register dq c byte write register dq b byte write register dq a byte write register enable register pipelined enable output registers sense amps memory array output buffers dq a byte write driver dq b byte write driver dq c byte write driver dq d byte write driver input registers a 0,a1,a a[1:0] sleep control zz e 2 dqs
cy7c1368 b document #: 38-05419 rev. ** page 3 of 17 pin configurations 2-chip enable 100-pin tqfp top view nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a nc nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d nc a a ce 1 ce 2 bw d bw c bw b bw a a v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1368b (256k x 32) nc a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a mode
cy7c1368 b document #: 38-05419 rev. ** page 4 of 17 3-chip enable pin configurations (continued) 100-pin tqfp top view nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a nc nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d nc a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1368b (256k x 32) nc a a a a a 1 a 0 nc nc v ss v dd nc a a a a a a a a mode
cy7c1368 b document #: 38-05419 rev. ** page 5 of 17 pin descriptions pin tqfp type description a 0 , a 1 , a 37, 36, 32,33,34, 35,44,45, 46,47,48, 49,50,80, 81,82,99, 100, 92 (ajc), 43 (ac) input- synchronous address inputs used to select one of the 256k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [1] are sampled active. a [1:0] are fed to the two-bit counter. bw a , bw b , bw c , bw d 93,94 input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk . gw 88 input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:d] and bwe ). bwe 87 input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk 89 input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 98 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 2 97 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 [2] 92 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. not available for aj package version. oe 86 input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments the address in a burst cycle. adsp 84 input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc 85 input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz 64 input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs 2,3, 6,7,8,9,12,13 ,18,19,22,23, 24,25,28,29, 52,53,56,57, 58,59,62,63, 68,69,72,73, 74,75.75,78, 79 i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs are placed in a tri-state condition. v dd 15,41,65, 91 power supply power supply inputs to the core of the device .
cy7c1368 b document #: 38-05419 rev. ** page 6 of 17 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the cy7c1368b supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3 and an asynchronous output enable (oe ) provide for easy bank selection and output three-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. the corre- sponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. the cy7c1368b is a double-cycle deselect part. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will three-state immediately after the next clock rise. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw [a:d] ) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqx inputs is written into the corre- sponding address location in the memory core. if gw is high, then the write operation is controlled by bwe and bw [a:d] signals. the cy7c1368b provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1368b is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will three-state the output drivers. as a safety precaution, dqs are automatically three-stated whenever a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:d] ) are asserted active to conduct a write to the desired byte(s). adsc triggered write accesses require a v ss 17,40,67, 90 ground ground for the core of the device . v ddq 4,11,20,27, 54,61,70, 77 i/o power supply power supply for the i/o circuitry . v ssq 5,10,21,26, 55,60,71, 76 i/o ground ground for the i/o circuitry . mode 31 input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc 1,16,30,38,3 9,42, 43(ajc),51, 66,80 no connects . not internally connected to the die. pin descriptions (continued) pin tqfp type description
cy7c1368 b document #: 38-05419 rev. ** page 7 of 17 single clock cycle to complete. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1368b is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. doing so will three-state the output drivers. as a safety precaution, dq x are automatically tri-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1368b provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specif- ically to support intel? pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. both read and write burst operations are supported asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 truth table [3, 4, 5, 6, 7] operation address used ce 1 ce 3 ce 2 zz adsp adsc adv write oe clk dq deselected cycle, power-down none h x x l x l x x x l-h three-state deselected cycle, power-down none l x l l l x x x x l-h three-state deselected cycle, power-down none l h x l l x x x x l-h three-state deselected cycle, power-down none l x l l h l x x x l-h three-state deselected cycle, power-down none l h x l h l x x x l-h three-state zz mode, power-down none x x x h x x x x x x three-state read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h three-state write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h three-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h three-state notes: 3. x = ?don't care.? h = logic high, l =logic low. 4. write =l when any one or more byte write enable signals (bw a, bw b, bw c, bw d ) and bwe =l or gw =l. write =h when all byte write enable signals ( bw a , bw b, bw c, bw d ), bwe , gw = h . 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a: d] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low).
cy7c1368 b document #: 38-05419 rev. ** page 8 of 17 read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h three-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h three-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h three-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d truth table for read/write [3, 4] function gw bwe bw a bw b bw c bw d read h h x x x x read h l h h h h write byte a - (dq a and dqp a )h l l h h h write byte b- (dq b and dqp b )h l h l h h write byte c- (dq c and dqp c )h l h h l h write byte d- (dq d and dqp d )h l h h h l write all bytes h l l l l l write all bytes l x x x x x zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 35 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz recovery time this parameter is sampled 2t cyc ns t rzzi zz inactive to exit snooze current this parameter is sampled 0 ns truth table (continued) [3, 4, 5, 6, 7] operation address used ce 1 ce 3 ce 2 zz adsp adsc adv write oe clk dq
cy7c1368 b document #: 38-05419 rev. ** page 9 of 17 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................... ?65c to +150 ambient temperature with power applied............................................. ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +4.6v dc voltage applied to outputs in tri-state ........................................... ?0.5v to v ddq +0.5v dc input voltage......................................?0.5v to v dd +0.5v current into outputs (low)......................................... 20 ma static discharge voltage............................................ >2001v (per mil-std-883,method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature (t a )v dd v ddq com?l 0c to +70c 3.3v ? 5%/+10% 3.3v ? 5% to v dd electrical characteristics over the operating range [8, 9] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 3.135 v dd v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ih input high voltage [8] v ddq = 3.3v 2.0 v dd + 0.3v v v il input low voltage [8] v ddq = 3.3v ?0.3 0.8 v i x input load current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 5.0 ns cycle, 200 mhz 220 ma 6.0 ns cycle, 166 mhz 180 ma i sb1 automatic ce power-down current?ttl inputs v dd = max., device deselected, v in v ih or v in v il , f = f max = 1/t cyc all speeds 50 ma i sb2 automatic ce power-down current?cmos inputs v dd = max., device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 30 ma i sb3 automatic ce power-down current?cmos inputs v dd = max., device deselected, or v in 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc all speeds 50 ma i sb4 automatic ce power-down current?ttl inputs v dd = max., device deselected, v in v ih or v in v il , f = 0 all speeds 40 ma notes: 8. overshoot: v ih (ac) < v dd +1.5v(pulse width less than t cyc /2), undershoot: v il (ac)> -2v(pulse width less than t cyc /2). 9. power-up: assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd .
cy7c1368 b document #: 38-05419 rev. ** page 10 of 17 thermal characteristics [10] parameter description test conditions tqfp package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 25 c/w jc thermal resistance (junction to case) 9c/w capacitance [10] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 3.3v 4pf c clk clock input capacitance 4 pf c i/o input/output capacitance 4 pf ac test loads and waveforms switching characteristics over the operating range [15, 16] parameter description 200 mhz 166 mhz unit min. max. min. max. t power v dd (typical) to the first access [11] 11ms clock t cyc clock cycle time 5.0 6.0 ns t ch clock high 2.0 2.4 ns t cl clock low 2.0 2.4 ns output times t co data output valid after clk rise 3.0 3.5 ns t doh data output hold after clk rise 1.25 1.25 ns t clz clock to low-z [12, 13, 14] 1.25 1.25 ns t chz clock to high-z [12, 13, 14] 1.25 3.0 1.25 3.5 ns t oev oe low to output valid 3.0 3.5 ns notes: 10. tested initially and after any design or process change that may affect these parameters. 11. this part has a voltage regulator internally; tpower is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 12. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 13. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 14. this parameter is sampled and not 100% tested. 15. timing reference level is 1.5v when v ddq = 3.3v. 16. test conditions shown in (a) of ac test loads unless otherwise noted. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v dd gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load
cy7c1368 b document #: 38-05419 rev. ** page 11 of 17 t oelz oe low to output low-z [12, 13, 14] 00ns t oehz oe high to output high-z [12, 13, 14] 3.0 3.5 ns set-up times t as address set-up before clk rise 1.5 1.5 ns t ads adsc , adsp set-up before clk rise 1.5 1.5 ns t advs adv set-up before clk rise 1.5 1.5 ns t wes gw , 0e , bw [a : d] set-up before clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t ces chip enable set-up before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 ns t advh adv hold after clk rise 0.5 0.5 ns t weh gw , bwe , bw [a : d] hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns switching characteristics over the operating range (continued) [15, 16] parameter description 200 mhz 166 mhz unit min. max. min. max.
cy7c1368 b document #: 38-05419 rev. ** page 12 of 17 switching waveforms read timing [17] note: 17. on this diagram, when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces g w, bwe,bw data out (q) high-z t doh t co adv t oehz t co single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address adv suspends burst don?t care undefined [a:d] clz t
cy7c1368 b document #: 38-05419 rev. ** page 13 of 17 write timing [17, 18] note: 18. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:d] low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw [a:d] adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined d(a1) high-z data in (d) d ata out (q)
cy7c1368 b document #: 38-05419 rev. ** page 14 of 17 read/write timing [17, 19, 20] notes: 19. the data bus (q) remains in tri-state following a write cycle unless a new read access is initiated by adsp or adsc . 20. gw is high . switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 bwe, bw [a:d] a3 don?t care undefined
cy7c1368 b document #: 38-05419 rev. ** page 15 of 17 ordering information speed [23] (mhz) ordering code package name package type operating range 166 CY7C1368B-166AC a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial 166 cy7c1368b-166ajc a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack notes: 21. device must be deselected when entering zz mode. see truth table for all possible signal conditions to deselect the device. 22. dqs are in tri-state when exiting zz sleep mode. 23. please contact your local cypress sales representative for availability of 200-mhz speed grade option. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only z z mode timing [21, 22]
cy7c1368 b document #: 38-05419 rev. ** page 16 of 17 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. intel and pentium are registered trademarks, and i486 is a tradem ark, of intel corporation. powerpc is a registered trademark of ibm. all product and company names mentioned in this document are the trademarks of their respective holders. package diagram 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
cy7c1368 b document #: 38-05419 rev. ** page 17 of 17 document history page document title: cy7c1368b 9m (256k x 32) pipelined dcd sync sram document number: 38-05419 rev. ecn no. issue date orig. of change description of change ** 130317 12/30/03 aju new data sheet

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